Research Experiences

* For reference numbers of "Related Publications" below, please refer to the "Publications" page.

Ongoing Research Projects

Optimization of Type-3 Compute Express Link (CXL) Add-In Card (AIC) Memory

  • Development of an in-house simulation platform for CXL memory devices

  • Characterizing the detailed performance of the CXL-attached system under various scenarios

  • Optimization of memory-centric workloads (e.g., NLP) on the CXL-attached system

  • Sponsor: SK Hynix, South Korea (Feb. 2022 - Jan. 2023)

  • Role: Research participant

Development of Open Convergence Memory Solution and Platform for Next-Generation Memories

  • Development of a high-performance and low-power PCM-based computer architecture for CNN inference

  • Sponsor: Ministry of Trade, Industry & Energy (MOTIE), South Korea (April. 2020 - Dec. 2023)

  • Related publications: [J7], [C3], [J6],[C4], [S1]

  • Role: Research participant

Past Research Projects

DRAM/PRAM heterogeneous memory architecture and controller IC design technology research and development

  • Development of FPGA-based heterogeneous memory system emulation platform

  • Construction of reliable PRAM technologies concerning endurance and write/read disturbance errors

  • Related Publications: [J2], [C2], [C3], [J6], [P3], [P4]

  • Sponsor: Ministry of Trade, Industry & Energy (MOTIE), South Korea (July. 2017 - Dec. 2021)

  • Role: Research participant

Architecture exploration of a hardwired PCM controller

  • Characterizing the performance in the in-house PCM controller simulator

  • Minimizing the performance overhead of accessing the DRAM-based address translation table (AIT) in the PCM controller

  • Related publications: [C4]

  • Sponsor: SK Hynix, South Korea (July. 2020 - June. 2021)

  • Role: Research participant

PRAM memory scheduler modeling and its verification against RTL

  • Development of an in-house and accurate PCM controller simulator (implemented with C++)

  • Validated functionality and cycle accuracy against the industrial RTL simulation trace

  • Sponsor: SK Hynix, South Korea(July. 2019 - June. 2020)

  • Role: Research participant

Schemes for managing metadata in PCRAM software wear-leveling

  • Development of PCRAM simulation environment using NVMain and gem5

  • Minimizing the performance overhead of read-modify-write module in a PCRAM system

  • Prolonging the lifetime of PCRAM with the table-based, static wear-leveling

  • Related publications: [J2], [J5], [P3]

  • Sponsor: SK Hynix, South Korea (July. 2017 - June. 2018)

  • Role: Research participant

Management on non-volatile memory systems

  • Hot address-based wear-leveling for PRAM

  • Related publications: [J1], [J4], [P1], [P2]

  • Sponsor: SK Hynix, South Korea (July. 2016 - June. 2017)

  • Role: Research participant

  • I joined this project from Sep. 2016

Development of parallel processing techniques for computational imaging

  • Development of an algorithm for improving the image quality under surgery environment

  • Acceleration of the above algorithm using FPGA

  • Related publications: [C1], [J3]

  • Sponsor: Korea Electrotechnology Research Institute (KERI), South Korea (Jan. 2016 - Nov. 2017)

  • Role: Research participant

  • I joined this project on Sep. 2016

Professional Activities


  • Program Committee, The 40th IEEE International Conference on Computer Design (ICCD) - 8 papers

  • Reviewer, Elsevier Microelectronics Journal - 2 papers

  • Reviewer, IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS) - 2 papers


  • First Prize in Haedong Best Paper Award (Academic Research Work)

  • Reviewer, Elsevier Materials Research Bulletin - 1 paper

  • Reviewer, IEEE /IEIE International Conference on Consumer Electronics Asia (ICCE-ASIA) - 20 papers

  • Reviewer, IEIE Transactions on Smart Processing and Computing - 1 paper